Digital IC Design Engineer with +8 years of industrial experience in ASIC and FPGA methodologies from RTL to GDS.

Strong foundation in RTL Design, functional verification with Verilog, VHDL and SystemVerilog with Mentor tools as well as Backend flow starting from Synthesis, Formal Verification, Place & Route, STA, Timing Closure, Physical Verification with Synopsys tools. I also worked with Xilinx and Altera FPGA designs as well as Veloce Emulation. I have good experience with Lab testing and Hardware debugging. I have good understanding of PCI Express 3.0 and 4.0 protocols. I have taken up leadership responsibility within the Digital Implementation team.